1. Field of the Invention
The present invention relates to a structure of an increased capacitance of a capacitor for a semiconductor device utilizing the capacitor for charge storage, such as a MOS dynamic RAM, and a method of manufacturing thereof.
2. Description of the Prior Art
FIG. 1 is a view showing a sectional structure of a conventional MOS dynamic RAM cell. In FIG. 1, a MOS transistor serving as a transfer gate is formed by comprising an impurity diffusion layer 5 as a source and a drain formed at the surface of a semiconductor substrate 1; a gate oxide film 6 formed in a predetermined region on the semiconductor substrate 1; and a gate electrode 7 formed on the gate oxide film 6. On the other hand, a capacitor portion is formed by comprising a dielectric film 3 formed in a predetermined region on the surface of the substrate 1 and a capacitor electrode 4 formed on the dielectric film 3. The MOS transistor and the capacitor portion constitute a MOS dynamic RAM cell. The MOS dynamic RAM cell is electrically insulated from an adjacent device by an isolation oxide film 2.
Now, referring to FIG. 1; the operation of the above described device will be described. With the structure shown in FIG. 1, a memory cell is formed. In this structure, a single bit information is stored in the cell by determining either one of the two states, that is, either the state in which electric charge is stored in the capacitor portion or the state in which electric charge is discharged from the capacitor portion. A more detailed description will be given in the following. The so-called MOS type capacitor is formed by the semiconductor substrate 1, the dielectric film 3 and the capacitor electrode 4. The capacitor electrode 4 is maintained at a fixed potential so that electric charge corresponding to the capacitance of the capacitor can be stored in the interface between the semiconductor substrate 1 and the dielectric film 3. The transfer gate (the MOS transistor) formed by the gate oxide film 6 and the gate electrode 7 is electrically opened or closed according to a potential at the gate electrode so that the electric charge is stored in the capacitor (namely, writing information is performed) or so that it is determined whether or not the electric charge is stored in the capacitor (namely, reading information is performed). A more detailed description of these operations, omitted from this specification since there is no relation with the subject of the present invention, can be seen for example in "Introduction to MOS LSI Design" written by J. Mavor et al., University of Edinburgh, translated into Japanese by T. Sugano et al., Sangyo Tosho Co. (1983).
Generally, in a MOS dynamic RAM, the charge amount stored in the capacitor portion corresponds to the intensity of the signal. In such a conventional memory device as described above, it is always necessary to fabricate a capacitor and a transistor in a fixed area and therefore, if the area occupied by a cell is made smaller as a result of an improvement of an integration degree of an LSI (Large Scale Integrated Circuit), the area of the capacitor becomes also smaller accordingly. As a result, serious defects are involved that the storage capacity of the capacitor is considerably decreased, causing lack of stability to noise in memory operation.
As the prior art aiming at correcting the above stated defects, the following documents are known:
"Novel High Density Stacked Capacitor MOS RAM" (#) by M. Koyanagi, H. Sunami and N. Hashimoto, Jap. J. Appl. Phys., Vol. 18, Supplement 18-1, pp. 35 to 42, 1979,
"A 64 Kbit MOS Dynamic RAM with Novel Memory Capacitor" (#) by F. Smith et al., IEEE Trans. Solid-State Circuits, Vol. SC-15, No. 2, April 1980, pp. 184 to 189,
"Quadruply Self-Aligned Stacked High-Capacitance RAM Using Ta.sub.2 O.sub.5 High-Density VLSI Dynamic Memory", IEEE Trans. Electron Devices, Vol. ED-29, No. 3 March 1982.
In all of these prior art documents, the storage capacity is increased by making a capacitor have a laminated structure. However, the method of forming a stacked capacitor disclosed in any of the above stated documents has a disadvantage that the laminated structure cannot include more than two layers.